Suite of AI Agents and Tools to Accelerate HDL Design
Hey YC! We're Tamzid and Rohil from SigmanticAI.
The Problem with Creating Custom Hardware
- HDL tooling hasn’t changed much since the '90s: still slow, manual, and fragmented
- Debugging eats up majority of hardware dev time
- There's no seamless AI-native experience for building and reasoning about HDL
Our Solution
SigmanticAI. What it can do:
- Natural language to synthesizable Verilog + testbenches
- RL-driven debugging loop
- Built-in onboarding, codebase annotation, and spec documentation generation
- LLM-powered on both cloud and fully air-gapped/on-prem deployments
- Seameless integration with VScode + your existing synthesis tools from Cadence, Synopsys, etc.
We’ve already made a RISCV CPU start to finish with it, onboarded our first paying customer, and are getting 90%+ accuracy on the VerilogEval benchmark (NVIDIA framework)
Demo video
https://youtu.be/Cq3hpMflIA8
Asks!
- We want to talk to:
- Anyone working with FPGAs, custom chips, ML accelerators, or RISC-V cores
- Anyone working in EDA
- Anyone working with fine tuned LLMs for hardware
- Try us out! Thank you!
Who We Are
We’ve spent years working on both LLMs and hardware. After working at Apple (Tamzid) and Amazon (Rohil) and research in FPGA mapping and LLaMA fine-tuning, we realized the real bottleneck in hardware design is tooling. We’ve built custom CPUs, worked with EDA stacks, and experienced the pain firsthand. Conversations with engineers at Northrop Grumman, SciEngines, and Quadric made it clear: hardware desperately needs a smarter workflow.
